The present disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly, to a charge trap type non-volatile memory device and a method for fabricating the same.
A non-volatile memory device refers to a memory device which can maintain stored data intact even when a power supply is cut off. In particular, a memory device which stores data by storing or erasing charges in a floating gate is referred to as a floating gate type non-volatile memory device.
A typical floating gate type non-volatile memory device includes a tunnel insulation layer, a floating gate, a charge barrier layer, and a control gate formed over a substrate. A typical floating gate type non-volatile memory device stores data by injecting or emitting charges in the floating gate.
However, there is a limitation as to achieving a large integration scale in a floating gate type non-volatile memory device because as the thickness of a tunnel insulation layer becomes greater, a higher operation voltage may be needed causing its peripheral circuitry to become complicated.
Therefore, a typical method presents a charge trap type non-volatile memory device as a type of non-volatile memory device. Herein, a charge trap type non-volatile memory device is described in detail with a drawing.
FIG. 1 illustrates a cross-sectional view of a typical charge trap type non-volatile memory device. The charge trap type non-volatile memory device includes a tunnel insulation layer 110, a charge trap layer 120, a charge barrier layer 130, a gate electrode 140, and a hard mask pattern 150 formed over a substrate 100.
The tunnel insulation layer 110 is formed as an energy barrier layer for charge tunneling. The tunnel insulation layer 110 may include an oxide-based layer.
The charge trap layer 120 stores charges which tunneled through the tunnel insulation layer 110. Thus, the charge trap layer 120 substantially functions as a data storing unit. The charge trap layer 120 may include a nitride-based layer.
The charge barrier layer 130 is formed to prevent charges from passing through the charge trap layer 120 and moving upward.
At this time, nitride-based spacers 160 are formed over sidewalls of the hard mask pattern 150 and the gate electrode 140 to prevent oxidation of the gate electrode 140 during a subsequent process.
Reference denotation ‘A’ represents a charge trap structure A which includes the tunnel insulation layer 110, the charge trap layer 120, the charge barrier layer 130, the gate electrode 140, the hard mask pattern 150, and the nitride-based spacers 160. An oxide-based spacer 170 is formed over the charge trap structure A.
The typical charge trap type non-volatile memory device having the above described structure stores or erases charges in a deep level trap site in the charge trap layer 120. Thus, the stored charges may not be lost even when the tunnel insulation layer 110 is formed to a small thickness. Also, the typical charge trap type non-volatile memory device may be operated at a low operation voltage. Furthermore, the integration scale of a semiconductor device may be improved compared to a floating gate type non-volatile memory device.
However, the typical charge trap type non-volatile memory device may have limitations as follows. For the charge trap layer 120 including a nitride-based layer, there may be a large density difference in a trap site depending on the composition of silicon (Si) and nitrogen (N) of the nitride-based layer. Thus, charges stored in the charge trap layer 120 may not be dispersed evenly.
In particular, storage and erasure of charges may not be performed smoothly because the trap site is concentrated on an interface between the charge barrier layer 130 and the charge trap layer 120 and the interface state is unstable. Such limitation may deteriorate data retention and endurance of the memory device.
Furthermore, sidewalls of the tunnel insulation layer 110 and the charge trap layer 120 are not protected by the nitride-based spacers 160. Therefore, the sidewalls of the tunnel insulation layer 110 and the charge trap layer 120 may be exposed and damaged during a subsequent process.
In the typical method, an oxidation process is performed on the substrate structure including the charge trap structure A to form the oxide-based spacer 170. The oxide-based spacer 170 is formed so that the tunnel insulation layer 110 and the charge trap layer 120 may be reinforced and prevented from getting damaged.
However, there are limitations as to preventing damage by forming the oxide-based spacer 170 on the sidewalls of the layers that constitute the charge trap structure A due to structural characteristics of the charge trap structure A configured in a multiple-layer stack structure. As a result, damage in the charge trap layer 120 may induce loss of data stored in the memory device, i.e., charges, and thus, deteriorate data retention of the memory device.
On the other hand, if the oxidation process is performed for a longer period of time in order to sufficiently reinforce the damaged sidewalls, there may arise other limitations such as oxidation of the substrate 100 or change in the impurity concentration level and depth in source/drain regions.
Furthermore, charges may be lost through a portion of the sidewall of the charge trap layer 120, as represented with reference denotation ‘B’, because an interface between the charge trap layer 120 and the oxide-based spacer 170 is not stabilized even after the oxide-based spacer 170 is formed over the sidewalls of the charge trap layer 120.